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Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontroller
OM5232
DESCRIPTION
The OM5232 Single-Chip 8-Bit Microcontroller is manufactured in an advanced CMOS process and is a derivative of the 80C51 microcontroller family. The OM5232 has the same instruction set as the 80C51. See also: - OM5202 -- ROMless version - OM5234 -- 16K bytes mask programmable ROM - OM5238 -- 32K bytes mask programmable ROM This device provides architectural enhancements that make it applicable in a variety of applications for general control systems. The OM5232 contains a non-volatile 8k x 8 read-only program memory, a volatile 256 x 8 read/write data memory, four 8-bit I/O ports, two 16-bit timer/event counters (identical to the timers of the 80C51), a multi-source, two-priority-level, nested interrupt structure, UART and on-chip oscillator and timing circuits. For systems that require extra capability, the OM5232 can be expanded using standard TTL compatible memories and logic. The device also functions as an arithmetic processor having facilities for both binary and BCD arithmetic plus bit-handling capabilities. The instruction set consists of over 100 instructions: 49 one-byte, 45 two-byte and 17 three-byte. With a 16MHz crystal, 58% of the instructions are executed in 0.75s and 40% in 1.5s. Multiply and divide instructions require 3s.
PIN CONFIGURATIONS
P1.0 1 P1.1 2 P1.2 3 P1.3 4 P1.4 5 P1.5 6 P1.6 7 P1.7 8 RST 9 RxD/P3.0 10 TxD/P3.1 11 INT0/P3.2 12 INT1/P3.3 13 T0/P3.4 14 T1/P3.5 15 WR/P3.6 16 RD/P3.7 17 XTAL2 18 XTAL1 19 VSS 20 DIP 40 V DD 39 P0.0/AD0 38 P0.1/AD1 37 P0.2/AD2 36 P0.3/AD3 35 P0.4/AD4 34 P0.5/AD5 33 P0.6/AD6 32 P0.7/AD7 31 EA 30 ALE 29 PSEN 28 P2.7/A15 27 P2.6/A14 26 P2.5/A13 25 P2.4/A12 24 P2.3/A11 23 P2.2/A10 22 P2.1/A9 21 P2.0/A8
FEATURES
* 80C51 central processing unit * 8k x 8 ROM, expandable externally to 64k bytes * 256 x 8 RAM, expandable externally to 64k bytes * Two standard 16-bit timer/counters * Four 8-bit I/O ports * Two open drain I/O's (P1.6, P1.7) * Full-duplex UART facilities * Power control modes
- Idle mode - Power-down mode
44
34
1
33
QFP (SOT307-2) 11 23
* ROM code protection * Extended frequency range: 1.2 to 16 MHz * Operating ambient temperature range: 0 to
PART NUMBER SELECTION
PHILIPS PART ORDER NUMBER PART MARKING OM5232/FBP/xxx 1)
12
22
+70C
SEE PAGE 2 FOR QFP PIN FUNCTIONS.
PACKAGE NUMBER SOT129
TEMPERATURE RANGE C, PACKAGE 0 to +70, Plastic Dual In-line Package, 40 leads 0 to +70, Plastic Quad Flat Pack, 44 leads
FREQUENCY MHz 1.2 to 16 1.2 to 16
OM5232/FBB/xxx 1) SOT307-2 NOTE: 1. xxx denotes the ROM code number.
EQUIVALENT TYPES
Details are as specified by the data sheet for the equivalent type: OM5202 = P80C652 without I2C function. OM5232 = P83C652 without I2C function. OM5234 = P83C654 without I2C function. OM5238 = P83C528 without I2C function.
December 1994 1
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontroller
OM5232
QFP PIN FUNCTIONS
44 34
LOGIC SYMBOL
VDDVSS ADDRESS AND DATA BUS ADDRESS BUS RST
1
33
QFP (SOT307-2) 11 23 ALTERNATE FUNCTIONS
XTAL1 XTAL2 EA PSEN ALE
12
22
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Function P1.5 P1.6 P1.7 RST P3.0/RxD VSS4 P3.1/TxD P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 P3.6/WR P3.7/RD XTAL2 XTAL1
Pin 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
Function VSS1 NC P2.0/A8 P2.1/A9 P2.2/A10 P2.3/A11 P2.4/A12 P2.5/A13 P2.6/A14 P2.7/A15 PSEN ALE VSS2 EA/VPP P0.7/AD7
Pin 31 32 33 34 35 36 37 38 39 40 41 42 43 44
Function P0.6/AD6 P0.5/AD5 P0.4/AD4 P0.3/AD3 P0.2/AD2 P0.1/AD1 P0.0/AD0 VDD VSS3 P1.0 P1.1 P1.2 P1.3 P1.4
RxD TxD INT0 INT1 T0 T1 WR RD
PORT 3
NOTE: 1. Due to EMC improvements, all VSS pins (6, 16, 28, 39) must be connected to VSS.
BLOCK DIAGRAM
FREQUENCY REFERENCE XTAL2 XTAL1 COUNTERS T0 T1
OSCILLATOR AND TIMING
PROGRAM MEMORY (8K x 8 ROM)
DATA MEMORY (256 x 8 RAM)
TWO 16-BIT TIMER/EVENT COUNTERS
CPU
INTERNAL INTERRUPTS
64K BYTE BUS EXPANSION CONTRTOL
PROGRAMMABLE I/O
PROG SERIAL PORT FULL DUPLEX UART SYNCHRONOUS SHIFT
INT0
INT1
CONTROL
PARALLEL PORTS, ADDRESS/DATA BUS AND I/O PINS
SERIAL IN
SERIAL OUT
EXTERNAL INTERRUPTS
SHARED WITH PORT 3
December 1994
2
PORT 2
PORT 1
PORT 0
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontroller
OM5232
PIN DESCRIPTIONS
PIN NUMBER MNEMONIC VSS VDD P0.0-0.7 DIP 20 40 39-32 QFP 6, 16, 28, 39 38 37-30 TYPE I I I/O NAME AND FUNCTION Ground: 0V reference. With the QFP package all VSS pins (VSS1 to VSS4) must be connected. Power Supply: This is the power supply voltage for normal, idle, and power-down operation. Port 0: Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that have 1s written to them float and can be used as high-impedance inputs. Port 0 is also the multiplexed low-order address and data bus during accesses to external program and data memory. In this application, it uses strong internal pull-ups when emitting 1s. Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups, except P1.6 and P1.7 which are open drain. Port 1 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 1 pins that are externally pulled low will source current because of the internal pull-ups. (See DC Electrical Characteristics: IIL). Alternate functions include: open drain output open drain output Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 2 pins that are externally being pulled low will source current because of the internal pull-ups. (See DC Electrical Characteristics: IIL). Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @DPTR). In this application, it uses strong internal pull-ups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOV @Ri), port 2 emits the contents of the P2 special function register. Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 3 pins that are externally being pulled low will source current because of the pull-ups. (See DC Electrical Characteristics: IIL). Port 3 also serves the special features of the 80C51 family, as listed below: RxD (P3.0): Serial input port TxD (P3.1): Serial output port INT0 (P3.2): External interrupt INT1 (P3.3): External interrupt T0 (P3.4): Timer 0 external input T1 (P3.5): Timer 1 external input WR (P3.6): External data memory write strobe RD (P3.7): External data memory read strobe Reset: A high on this pin for two machine cycles while the oscillator is running, resets the device. An internal diffused resistor to VSS permits a power-on reset using only an external capacitor to VDD. Address Latch Enable: Output pulse for latching the low byte of the address during an access to external memory. In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator frequency. Note that one ALE pulse is skipped during each access to external data memory. Program Store Enable: Read strobe to external program memory via Port 0 and Port 2. It is activated twice each machine cycle during fetches from the external program memory. When executing out of external program memory two activations of PSEN are skipped during each access to external data memory. PSEN is not activated (remains HIGH) during no fetches from external program memory. PSEN can sink/source 8 LSTTL inputs and can drive CMOS inputs without external pull-ups. External Access: If during a RESET, EA is held at TTL, level HIGH, the CPU executes out of the internal program memory ROM provided the Program Counter is less than 16384. If during a RESET, EA is held a TTL LOW level, the CPU executes out of external program memory. EA is not allowed to float. Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock generator circuits. Crystal 2: Output from the inverting oscillator amplifier.
P1.0-P1.5
1-6
40-44, 1
I/O
P1.6 P1.7 P2.0-P2.7
7 8 21-28
2 3 18-25
I/O I/O I/O
P3.0-P3.7
10-17
5, 7-13
I/O
10 11 12 13 14 15 16 17 RST 9
5 7 8 9 10 11 12 13 4
I O I I I I O O I
ALE
30
27
I/O
PSEN
29
26
O
EA
31
29
I
XTAL1 XTAL2
19 18
15 14
I O
NOTE: To avoid "latch-up" effect at power-on, the voltage on any pin at any time must not be higher than VDD + 0.5V or VSS - 0.5V, respectively.
December 1994
3
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontroller
OM5232
Table 1.
SYMBOL ACC* B* DPTR: DPH DPL
OM5232 Special Function Registers
DESCRIPTION Accumulator B Register Data Pointer (2 bytes) Data Pointer High Data Pointer Low DIRECT BIT ADDRESS, SYMBOL, OR ALTERNATIVE PORT FUNCTION ADDRESS MSB LSB E0H F0H E7 F7 E6 F6 E5 F5 E4 F4 E3 F3 E2 F2 E1 F1 E0 F0 RESET VALUE 00H 00H
83H 82H AF AE AD ES1 BE BD PS1 86 AD6 96 SCL A6 A14 B6 WR - 9E SM1 A5 A13 B5 T1 - 9D SM2 A4 A12 B4 T0 - 9C REN A3 A11 B3 INT1 GF1 9B TB8 A2 A10 B2 INT0 GF0 9A RB8 A1 A9 B1 TXD PD 99 TI A0 A8 B0 RXD IDL 98 RI 85 AD5 95 AC ES0 BC PS0 84 AD4 94 AB ET1 BB PT1 83 AD3 93 AA EX1 BA PX1 82 AD2 92 A9 ET0 B9 PT0 81 AD1 91 A8 EX0 B8 PX0 80 AD0 90
00H 00H
IE*#
Interrupt Enable
A8H
EA BF
0x000000B
IP*#
Interrupt Priority
B8H
- 87
xx000000B
P0*
Port 0
80H
AD7 97
FFH
P1*#
Port 1
90H
SDA A7
FFH
P2*
Port 2
A0H
A15 B7
FFH
P3* PCON
Port 3 Power Control
B0H 87H
RD SMOD 9F
FFH 0xxx0000B
S0CON*# S0BUF#
Serial 0 Port Control Serial 0 Data Buffer
98H 99H
SM0
00H xxxxxxxxB
D7 PSW* Program Status Word reserved (Note 1) SP Stack Pointer reserved (Note 1) D0H DAH 81H DBH CY
D6 AC
D5 F0
D4 RS1
D3 RS0
D2 OV
D1 F1
D0 P 00H 00H 07H 00H
reserved (Note 1)
D9H
F8H
reserved (Note 1)
D8H 8F 8E TR1 8D TF0 8C TR0 8B IE1 8A IT1 89 IE0 88 IT0
00000000B
TCON* TH1 TH0 TL1 TL0 TMOD *
Timer Control Timer High 1 Timer High 0 Timer Low 1 Timer Low 0 Timer Mode
88H 8DH 8CH 8BH 8AH 89H
TF1
00H 00H 00H 00H 00H
GATE
C/T
M1
M0
GATE
C/T
M1
M0
00H
SFRs are bit addressable.
# SFRs are modified from or added to the 80C51 SFRs. NOTE 1. Reserved for I2C; not supported in OM5232
December 1994
4
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontroller
OM5232
ROM CODE PROTECTION
The OM5232 has an additional security feature. ROM code protection may be selected by setting a mask-programmable security bit (i.e., user dependent). This feature may be requested during ROM code submission. When selected, the ROM code is protected and cannot be read out at any time by any test mode or by any instruction in the external program memory space. The MOVC instructions are the only instructions that have access to program code in the internal or external program memory. The EA input is latched during RESET and is "don't care" after RESET (also if the security bit is not set). This implementation prevents reading internal program code by switching from external program memory to internal program memory during a MOVC instruction or any other instruction that uses immediate data.
Reset
A reset is accomplished by holding the RST pin high for at least two machine cycles (24 oscillator periods), while the oscillator is running. To insure a good power-on reset, the RST pin must be high long enough to allow the oscillator time to start up (normally a few milliseconds) plus two machine cycles. At power-on, the voltage on VDD and RST must come up at the same time for a proper start-up.
Idle Mode
In the idle mode, the CPU puts itself to sleep while all of the on-chip peripherals stay active. The instruction to invoke the idle mode is the last instruction executed in the normal operating mode before the idle mode is activated. The CPU contents, the on-chip RAM, and all of the special function registers remain intact during this mode. The idle mode can be terminated either by any enabled interrupt (at which time the process is picked up at the interrupt service routine and continued), or by a hardware reset which starts the processor in the same manner as a power-on reset.
OSCILLATOR CHARACTERISTICS
XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier. The pins can be configured for use as an on-chip oscillator, as shown in the Logic Symbol, page 2. To drive the device from an external clock source, XTAL1 should be driven while XTAL2 is left unconnected. There are no requirements on the duty cycle of the external clock signal, because the input to the internal clock circuitry is through a divide-by-two flip-flop. However, minimum and maximum high and low times specified in the data sheet must be observed.
Power-Down Mode
In the power-down mode, the oscillator is stopped and the instruction to invoke power-down is the last instruction executed. Only the contents of the on-chip RAM are preserved. A hardware reset is the only way to terminate the power-down mode. The control bits for the reduced power modes are in the special function register PCON. Table 2 shows the state of the I/O ports during low current operating modes.
Table 2.
MODE Idle Idle
External Pin Status During Idle and Power-Down Mode
PROGRAM MEMORY Internal External Internal External ALE 1 1 0 0 PSEN 1 1 0 0 PORT 0 Data Float Data Float PORT 1 Data Data Data Data PORT 2 Data Address Data Data PORT 3 Data Data Data Data
Power-down Power-down
Serial Control Register (S1CON) - See Table 3
S1CON (D8H) CR2 ENS1 STA STO SI AA CR1 CR0
Bits CR0, CR1 and CR2 determine the serial clock frequency that is generated in the master mode of operation.
Table 3.
CR2
0 0 0 0 1 1 1 1
Serial Clock Rates
BIT FREQUENCY (kHz) AT fOSC CR1
0 0 1 1 0 0 1 1
CR0
0 1 0 1 0 1 0 1
6MHz 23 27 31.25 37 6.25 50 100 0.24 < 62.5 0 to 255
12MHz 47 54 62.5 75 12.5 100 200 0.49 < 62.5 0 to 254
16MHz 62.5 71 83.3 100 17 133 267 0.65 < 55.6 0 to 253
fOSC DIVIDED BY 256 224 192 160 960 120 60 96 x (256 - (reload value Timer 1)) reload value range Timer 1 (in mode 2)
December 1994
5
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontroller
OM5232
ABSOLUTE MAXIMUM RATINGS1, 2, 3
PARAMETER Storage temperature range Voltage on any other pin to VSS Input, output current on any single pin Power dissipation (based on package heat transfer limitations, not device power consumption) RATING -65 to +150 -0.5 to + 6.5 5 1 UNIT C V mA W
NOTES: 1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any conditions other than those described in the AC and DC Electrical Characteristics section of this specification is not implied. 2. This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maxima. 3. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless otherwise noted.
40 IDD (mA)
30
(1)
20
10
(2)
0
0
4
8
12 fXTAL1 (MHz)
16
(1) MAXIMUM OPERATING MODE: VDD = VDDmax (2) MAXIMUM IDLE MODE: VDD = VDDmax These values are valid within the specified frequency range.
Figure 1. IDD vs. Frequency
December 1994
6
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontroller
OM5232
DC ELECTRICAL CHARACTERISTICS
VSS = 0V, VDD = 5.0V 10%. Operating temperature range 0 to 70C. TEST SYMBOL VIL VIL1 VIL2 VIH VIH1 VIH2 VOL VOL1 VOL2 VOH PARAMETER Input low voltage, except EA, P1.6, P1.7 Input low voltage to EA Input low voltage to P1.6, P1.7 Input high voltage, except XTAL1, RST, P1.6, P1.7 Input high voltage, XTAL1, RST Input high voltage, P1.6, P1.7 Output low voltage, ports 1, 2, 3, except P1.6, P1.7 Output low voltage, port 0, ALE, PSEN Output low voltage, P1.6, P1.7 Output high voltage, ports 1, 2, 3, ALE, PSEN 9) IOL = 1.6mA 7), 8) IOL = 3.2mA
7), 8)
LIMITS MIN. -0.5 -0.5 -0.5 0.2VDD+0.9 0.7VDD 0.7VDD MAX. 0.2VDD-0.1 0.2VDD-0.3 0.3VDD VDD+0.5 VDD+0.5 6.0 0.45 0.45 0.4 2.4 0.75VDD 0.9VDD 2.4 0.75VDD 0.9VDD -50 -650 10 10 UNIT V V V V V V V V V V V V V V V A A A A
CONDITIONS
IOL = 3.0mA IOH = -60A IOH = -25A IOH = -10A IOH = -800A IOH = -300A IOH = -80A
VOH1
Output high voltage; port 0 in external bus mode
IIL ITL IL1 IL2 IDD
Logical 0 input current, ports 1, 2, 3, except P1.6, P1.7 Logical 1-to-0 transition current, ports 1, 2, 3, except P1.6, P1.7 Input leakage current, port 0, EA Input leakage current, P1.6, P1.7 Power supply current: Active mode @ 16MHz 2), 10) Idle mode @ 16MHz 3), 10) Power down mode 4), 5) Internal reset pull-down resistor Pin capacitance
VIN = 0.45V See note 6) 0.45V < VI < VDD 0V < VI < 6.0V 0V < VDD < 6.0V See note 1) VDD=6.0V
26.5 6 50 50 150 10
mA mA A k pF
RRST CIO
Freq.=1MHz
NOTES FOR DC ELECTRICAL CHARACTERISTICS: 1. See Figures 9 through 11 for IDD test conditions. 2. The operating supply current is measured with all output pins disconnected; XTAL1 driven with tr = tf = 5ns; VIL = VSS + 0.5V; VIH = VDD -0.5V; XTAL2 not connected; EA = RST = Port 0 = P1.6 = P1.7 = VDD. See Figure 9. 3. The idle mode supply current is measured with all output pins disconnected; XTAL1 driven with tr = tf = 5ns; VIL = VSS + 0.5V; VIH = VDD -0.5V; XTAL2 not connected; Port 0 = P1.6 = P1.7 = VDD; EA = RST = VSS. See Figure 10. 4. The power-down current is measured with all output pins disconnected; XTAL2 not connected; Port 0 = P1.6 = P1.7 = VDD; EA = RST = VSS. See Figure 11. 5. 2V VPD VDDmax. 6. Pins of ports 1 , 2, and 3 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its maximum value when VIN is approximately 2V. 7. Capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the VOLs of ALE and ports 1 and 3. The noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operations. In the worst cases (capacitive loading > 100pF), the noise pulse on the ALE pin may exceed 0.8V. In such cases, it may be desirable to qualify ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input. 8. Under steady state (non-transient) conditions, IOL must be externally limited as follows: Maximum IOL = 10mA per port pin; Maximum IOL = 26mA total for Port 0; Maximum IOL = 15mA total for Ports 1, 2, and 3; Maximum IOL = 71mA total for all output pins. If IOL exceeds the test conditions, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions. 9. Capacitive loading on ports 0 and 2 may cause the VOH on ALE and PSEN to momentarily fall below the 0.9VDD specification when the address bits are stabilizing. 10. IDDMAX for other frequencies can be derived from Figure 1, where FREQ is the external oscillator frequency in MHz. IDDMAX is given in mA.
December 1994
7
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontroller
OM5232
AC ELECTRICAL CHARACTERISTICS1, 2
16MHz CLOCK SYMBOL 1/tCLCL tLHLL tAVLL tLLAX tLLIV tLLPL tPLPH tPLIV tPXIX tPXIZ tAVIV tPLAZ Data Memory tRLRH tWLWH tRLDV tRHDX tRHDZ tLLDV tAVDV tLLWL tAVWL tQVWX tDW tWHQX tRLAZ tWHLH Shift Register tXLXL tQVXH tXHQX tXHDX tXHDV External Clock tCHCX tCLCX tCLCH tCHCL 6 6 6 6 High time3 Low time3 Rise time3 Fall time3 20 20 20 20 20 20 tCLCL - tCLCX tCLCL - tCHCX 20 20 ns ns ns ns 5 5 5 5 5 Serial port clock cycle time3 Output data setup to clock rising edge3 edge3 Output data hold after clock rising edge3 Input data hold after clock rising Clock rising edge to input data valid3 0.75 492 80 0 492 12tCLCL 10tCLCL-133 2tCLCL-117 0 10tCLCL-133 3, 4 3, 4 3, 4 3, 4 3, 4 3, 4 3, 4 3, 4 3, 4 3, 4 3, 4 3, 4 3, 4 3, 4 RD pulse width WR pulse width RD low to valid data in Data hold after RD Data float after RD ALE low to valid data in Address to valid data in ALE low to RD or WR low Address valid to WR low or RD low Data valid to WR transition Data setup time before WR Data hold after WR RD low to address float RD or WR high to ALE high 23 138 120 3 288 13 0 103 tCLCL-40 0 55 350 398 238 3tCLCL-50 4tCLCL-130 tCLCL-60 7tCLCL-150 tCLCL-50 0 tCLCL+40 275 275 148 0 2tCLCL-70 8tCLCL-150 9tCLCL-165 3tCLCL+50 6tCLCL-100 6tCLCL-100 5tCLCL-165 ns ns ns ns ns ns ns ns ns ns ns ns ns ns FIGURE 2 2 2 2 2 2 2 2 2 2 2 2 PARAMETER Oscillator frequency ALE pulse width Address valid to ALE low Address hold after ALE low ALE low to valid instruction in ALE low to PSEN low PSEN pulse width PSEN low to valid instruction in Input instruction hold after PSEN Input instruction float after PSEN Address to valid instruction in PSEN low to address float 0 38 208 10 23 143 83 0 tCLCL-25 5tCLCL-105 10 85 8 28 150 tCLCL-40 3tCLCL-45 3tCLCL-105 MIN MAX VARIABLE CLOCK MIN 1.2 2tCLCL-40 tCLCL-55 tCLCL-35 4tCLCL-100 MAX 16 UNIT MHz ns ns ns ns ns ns ns ns ns ns ns
s
ns ns ns ns
NOTES: 1. Parameters are valid over operating temperature range unless otherwise specified. 2. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF. 3. These values are characterized but not 100% production tested.
December 1994
8
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontroller
OM5232
EXPLANATION OF THE AC SYMBOLS
Each timing symbol has five characters. The first character is always `t' (= time). The other characters, depending on their positions, indicate the name of a signal or the logical status of that signal. The designations are: A - Address C - Clock D - Input data H - Logic level high I - Instruction (program memory contents) L - Logic level low, or ALE P - PSEN Q - Output data R - RD signal t - Time V - Valid W - WR signal X - No longer a valid logic level Z - Float Examples: tAVLL = Time for address valid to ALE low. tLLPL = Time for ALE low to PSEN low.
tLHLL
ALE
tAVLL
PSEN
tPLPH tLLPL tLLIV tPLIV tLLAX tPLAZ tPXIX
INSTR IN
tPXIZ
PORT 0
A0-A7
A0-A7
tAVIV
PORT 2 A8-A15 A8-A15
Figure 2. External Program Memory Read Cycle
ALE
tWHLH
PSEN
tLLDV tLLWL
RD
tRLRH
tAVLL
PORT 0 A0-A7 FROM RI OR DPL
tLLAX
tRLDV tRLAZ tRHDX
DATA IN
tRHDZ
A0-A7 FROM PCL
INSTR IN
tAVWL tAVDV
PORT 2 P2.0-P2.7 OR A8-A15 FROM DPH A8-A15 FROM PCH
Figure 3. External Data Memory Read Cycle
December 1994
9
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontroller
OM5232
ALE
tWHLH
PSEN
tLLWL
WR
tWLWH
tAVLL
PORT 0
tLLAX
tQVWX tDW
tWHQX
A0-A7 FROM RI OR DPL
DATA OUT
A0-A7 FROM PCL
INSTR IN
tAVWL
PORT 2
P2.0-P2.7 OR A8-A15 FROM DPH
A8-A15 FROM PCH
Figure 4. External Data Memory Write Cycle
INSTRUCTION ALE
0
1
2
3
4
5
6
7
8
tXLXL
CLOCK
tQVXH
OUTPUT DATA WRITE TO SBUF
tXHQX
tXHDV
INPUT DATA VALID CLEAR RI VALID
tXHDX
SET TI VALID VALID VALID VALID VALID VALID
SET RI
Figure 5. Shift Register Mode Timing
VIH1 0.8V
tCHCL
tCLCX tCLCL
tCHCX tCLCH
Figure 6. External Clock Drive at XTAL1
December 1994
10
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontroller
OM5232
VDD-0.5
0.2VDD+0.9 VLOAD 0.2VDD-0.1
VLOAD+0.1V VLOAD-0.1V
TIMING REFERENCE POINTS
VOH-0.1V VOL+0.1V
0.45V NOTE:
AC INPUTS DURING TESTING ARE DRIVEN AT VDD-0.5 FOR A LOGIC '1' AND 0.45V FOR A LOGIC '0'. TIMING MEASUREMENTS ARE MADE AT VIH MIN FOR A LOGIC '1' AND VIL MAX FOR A LOGIC '0'.
NOTE: FOR TIMING PURPOSES, A PORT IS NO LONGER FLOATING WHEN A 100MV CHANGE FROM LOAD VOLTAGE OCCURS, AND BEGINS TO FLOAT WHEN A 100mV CHANGE FROM THE LOADED VOH/VOL LEVEL OCCURS. IOH/IOL > + 20mA.
Figure 7. AC Testing Input/Output
Figure 8. Float Waveform
VDD IDD VDD VDD P0 EA (NC) CLOCK SIGNAL XTAL2 XTAL1 VSS P1.6 P1.7 VDD RST EA P0 VDD
VDD IDD
VDD
RST
* *
(NC) CLOCK SIGNAL
XTAL2 XTAL1 VSS
P1.6 P1.7
* *
Figure 9. IDD Test Condition, Active Mode All other pins are disconnected
Figure 10. IDD Test Condition, Idle Mode All other pins are disconnected
VDD IDD VDD RST EA P0 VDD
(NC)
XTAL2 XTAL1 VSS
P1.6 P1.7
* *
Figure 11. IDD Test Condition, Power Down Mode All other pins are disconnected. VDD = 2V to 5.5V NOTE: * Ports 1.6 and 1.7 should be connected to VCC through resistors of sufficiently high value such that the sink current into these pins does not exceed the IOL1 specification.
December 1994
11

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